67f5dfbe50
主要功能: - 修改RequirementModal支持12个订单班选择 - 添加OrderClassIconMap图标映射组件 - Store中添加selectedOrderClass状态管理 - WorkflowPage支持传递orderClass参数 - web_result添加URL参数切换功能 - 创建order-class-handler.js动态处理页面主题 技术改进: - 创建软链接关联订单班数据目录 - 生成wenlu.json和food.json数据结构 - 删除重复的web_result目录 - 添加测试页面test-order-class.html 影响范围: - 展会策划系统现支持12个订单班 - 结果展示页面自动适配不同订单班主题 - 用户可选择不同行业生成对应方案 🤖 Generated with Claude Code Co-Authored-By: Claude <noreply@anthropic.com>
72 lines
2.9 KiB
JavaScript
72 lines
2.9 KiB
JavaScript
/*
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Language: VHDL
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Author: Igor Kalnitsky <igor@kalnitsky.org>
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Contributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guillaume.savaton@eseo.fr>
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Description: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.
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Website: https://en.wikipedia.org/wiki/VHDL
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*/
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function vhdl(hljs) {
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// Regular expression for VHDL numeric literals.
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// Decimal literal:
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const INTEGER_RE = '\\d(_|\\d)*';
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const EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;
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const DECIMAL_LITERAL_RE = INTEGER_RE + '(\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';
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// Based literal:
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const BASED_INTEGER_RE = '\\w+';
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const BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';
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const NUMBER_RE = '\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';
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return {
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name: 'VHDL',
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case_insensitive: true,
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keywords: {
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keyword:
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'abs access after alias all and architecture array assert assume assume_guarantee attribute ' +
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'begin block body buffer bus case component configuration constant context cover disconnect ' +
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'downto default else elsif end entity exit fairness file for force function generate ' +
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'generic group guarded if impure in inertial inout is label library linkage literal ' +
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'loop map mod nand new next nor not null of on open or others out package parameter port ' +
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'postponed procedure process property protected pure range record register reject ' +
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'release rem report restrict restrict_guarantee return rol ror select sequence ' +
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'severity shared signal sla sll sra srl strong subtype then to transport type ' +
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'unaffected units until use variable view vmode vprop vunit wait when while with xnor xor',
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built_in:
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'boolean bit character ' +
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'integer time delay_length natural positive ' +
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'string bit_vector file_open_kind file_open_status ' +
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'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' +
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'std_ulogic std_ulogic_vector unresolved_unsigned u_unsigned unresolved_signed u_signed ' +
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'real_vector time_vector',
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literal:
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'false true note warning error failure ' + // severity_level
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'line text side width' // textio
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},
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illegal: /\{/,
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contains: [
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hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.
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hljs.COMMENT('--', '$'),
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hljs.QUOTE_STRING_MODE,
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{
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className: 'number',
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begin: NUMBER_RE,
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relevance: 0
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},
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{
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className: 'string',
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begin: '\'(U|X|0|1|Z|W|L|H|-)\'',
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contains: [ hljs.BACKSLASH_ESCAPE ]
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},
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{
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className: 'symbol',
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begin: '\'[A-Za-z](_?[A-Za-z0-9])*',
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contains: [ hljs.BACKSLASH_ESCAPE ]
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}
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]
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};
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}
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module.exports = vhdl;
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